Incorporating Effects of Process, Voltage, and Temperature Variation in BTI Model for Circuit Design

Bias Temperature Instability (BTI) is a major reliability issue in Nano-scale CMOS circuits. BTI effect results in the threshold voltage increase of MOS devices over time. Given the Process, Voltage, and Temperature (PVT) dependence of BTI effect, and the significant amount of PVT variations in Nano-scale CMOS, we propose a method of combining the effects of PVT variations and the BTI effect for circuit analysis. We investigate the PVT dependence of BTI effect on a ring oscillator circuit as a test bench for logic circuits and an SRAM cell as a test bench for memory circuits. The results show that low threshold voltage circuits at high temperature experiences the worst impact of aging effects. However, the bias dependence of the impact of aging effects on circuits may vary from circuit to circuit and from metric to metric depending how the sensitivity of the circuit to BTI threshold voltage shift at different biasing changes. KeywordsAging effects; Nano-scale CMOS; Process variations; Voltage variations; Temperature variations